Generic Compatible 40GBASE-SR QSFP+ 850nm 150m DOM MPO8/12 MMF Optical Transceiver Module

QSFP+40-85-015(SR)-MPO8/12

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  • Broad Multi-Brand Compatibility
  • Flexible Customization Support
  • Tested for Reliable Performance
  • Fast Response & Delivery
  • Professional Technical Support
产品展示
FC-LINK QSFP+ 40G 850nm 150m SR MPO 8/12 收发器采用 12 芯 MTP/MPO 公头连接器,支持 OM4 多模光纤上最远 150 米的链路和 OM3 多模光纤上最远 100 米的链路。它符合 QSFP+ MSA 和 IEEE 802.3ba 40GBASE-SR4 标准,并支持 4x10GBASE-SR 分支。该收发器与标准 40GBASE-SR4 接口完全兼容,并可根据 QSFP+ MSA 规范通过 I2C 接口提供数字诊断功能,从而实时访问运行参数。其热插拔和易于安装的设计使其非常适合各种应用,包括园区网络、数据中心、云部署、高性能计算 (HPC) 环境以及交换机、路由器、服务器和传输设备之间的互连。

 

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SPECIFICATIONS
Product ModelQSFP+40-85-015(SR)-MPO8/12Manufacturer BrandFC-LINK
Package TypeQSFP+Optical ConnectorMPO 8C/12C
Max Data Rate40GChannel Data Rate10.3125Gbps
Effective transmission distance(OM3)100mEffective transmission distance(OM4)150m
Wavelength850nmOperating Voltage3.3V
Fiber TypeMMFCore Size50/125µm
Transmitter TypeVCSELReceiver TypePIN
TX Power-7.6~2.4dbmReceiver Sensitivity-5.4dbm
Digital Diagnostic Monitoring(DDM)YESReceiver Overload2.4dBm
Power Consumption< 1.5WProtocolsIEEE 802.3ba
IEEE 802.3ae
QSFP+ MSA SFF-8436
Operating temperature(Commercial)0℃~+70℃Storage Temperature(Commercial)-40℃~+85℃

 

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Server-to-Switch Data Center Links
Used for 10G/25G/100G optical uplinks between servers and top-of-rack switches in high-density data center deployments.

Building-to-Building Campus Backbone
Suitable for 1G/10G fiber links between office buildings, campus distribution rooms, and backbone aggregation points.

Access-to-Core Enterprise Uplinks
Designed for switch uplinks from access to aggregation or core layers in enterprise and campus network architectures.

Industrial Switching in Harsh Environments
Applied in industrial Ethernet, automation systems, and outdoor cabinets where wider temperature tolerance and stable fiber communication are required.

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Compatible Brands
Cisco, Huawei, H3C, Juniper, Arista, Dell, Intel, Mellanox, HP, TP-Link (长条状展示品牌)

Customization Options

  • Vendor Coding
  • Private Label
  • Custom Part Number
  • Packaging Design

Temperature Grade Selectio

 

PERFORMANCE PARAMETER
Absolute Maximum Ratings
Parameter Symbol Min. Max. Unit
Storage Temperature TS -40 +85 °C
Supply Voltage VCC -0.5 3.6 V
Operating Relative Humidity RH 5 85 %
  *Exceeding any one of these values may destroy the device immediately.

 

Recommended Operating Conditions
Parameter Symbol Min. Typical Max. Unit
Operating Case Temperature Tc QSFP+40-85-015(SR)-MPO8/12 0 - +70 °C
Power Supply Voltage Vcc 3.135 3.3 3.465 V
Power Supply Current Icc - - 450 mA
Aggregate Bit Rate BRAVE - 41.25 - Gbps
Lane Bit Rate BRLANE - 10.3125 - Gbps

 

Optical and Electrical Characteristics
Parameter
Symbol
Min. Typical Max. Unit
OM3 MMF L 0.5 - 100 m
Aggregate Bit Rate BRAVE - 40 - Gbps
Per Lane Bit Rate BRLANE - 10.3125 - Gbps
Transmitter
Center Wavelength λC 840 850 860 nm
RMS Spectral Width RMS - - 0.65 nm
Average Launch Power, Each Lane Pout/lane -7.6 - 2.4 dBm
Transmit OMA, Per Lane TX_OMA/lane -5.6 - 3 dBm
Difference in Launch Power Between Any Two Lanes(OMA) - - - 4 dB
Peak Power, Each Lane - - - 4 dBm
Transmitter and Dispersion Penalty,Each Lane TDP/lane - - 3.5 dB
Extinction Ratio ER 3 - - dB
Optical Return Loss Tolerance -
-
-
12 dB
Average Launch Power of OFF, Each Lane - - - -30 dBm
Output Optical Eye     IEEE 802.3ba-2010 Compliant
Receiver
Center Wavelength λC 840 850 860 nm
Damage Threshold - 3.4 - - dB
Stressed Receiver Sensitivity in OMA,Each Lane Pmins - - -5.4 dBm
Maximum Receive Power, Each Lane Pmax - - 2.4 dBm
Average Power, Each Lane RX/lane -9.5 - +2.4 dBm
LOS De-Assert, OMA LOSD -    - -7.5 dBm
Receiver Reflectance Rr -    - -12 dB
LOS Assert LOSA -30    - - dBm
LOS Hysteresis - 0.5    - - dB

 

QSFP+ TRANSCEIVER ELECTRICAL PAD LAYOUT

 

PIN ARRANGEMENT AND DEFINITION
PIN ARRANGEMENT AND DEFINITION
Pin Logic Symbol Description Plug Sequence Notes
1 - GND Ground 1 1
2 CML-I Tx2n Transmitter Inverted Data Input 3 -
3 CML-I Tx2p Transmitter Non-Inverted Data Input 3 -
4 - GND Ground 1 1
5 CML-I Tx4n Transmitter Inverted Data Input 3 -
6 CML-I Tx4p Transmitter Non-Inverted Data Input 3 -
7 - GND Ground 1 1
8 LVTTL-I ModSelL Module Select 3 -
9 LVTTL-I ResetL Module Reset 3 -
10 - VccRx +3.3V Power Supply Receiver 2 2
11 LVCMOS- I/O SCL 2-wire Serial Interface Clock 3 -
12 LVCMOS- I/O SDA 2-wire Serial Interface Data 3 -
13 - GND Ground 1 1
14 CML-O Rx3p Receiver Non-Inverted Data Output 3 -
15 CML-O Rx3n
Receiver Inverted Data Output
3 -
16 - GND Ground 1 1
17 CML-O Rx1p Receiver Non-Inverted Data Output 3 -
18 CML-O Rx1n Receiver Inverted Data Output 3 -
19 - GND Ground 1 1
20 - GND Ground 1 1
21 CML-O Rx2n Receiver Inverted Data Output 3 -
22 CML-O Rx2p Receiver Non-Inverted Data Output 3 -
23 - GND Ground 1 1
24 CML-O Rx4n Receiver Inverted Data Output 3 -
25 CML-O Rx4p Receiver Non-Inverted Data Output 3 -
26 - GND Ground 1 1
27 LVTTL-O ModPrsL Module Present 3 -
28   LVTTL-O   IntL   Interrupt 3 -
29 - VccTx +3.3V Power supply transmitter 2 2
30 - Vcc1 +3.3V Power supply 2 2
31   LVTTL-I   LPMode   Low Power Mode 3 -
32 - GND Ground 1 1
33 CML-I Tx3p Transmitter Non-Inverted Data Input 3 -
34 CML-I Tx3n Transmitter Inverted Data Input 3 -
35 - GND Ground 1 1
36 CML-I Tx1p Transmitter Non-Inverted Data Input 3 -
37 CML-I Tx1n Transmitter Inverted Data Input 3 -
38 - GND Ground 1 1
1: GND is the symbol for signal and supply (power) common for the QSFP+ module. All are common within the QSFP+ module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common ground plane.
2: Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and shall be applied concurrently. Vcc Rx Vcc1 and Vcc Tx may be internally connected within the QSFP+ Module in any combination. The connector pins are each rated for a maximum current of 500mA.